1. Field of the Invention
This invention relates to package-level failure analysis and, more particularly, to defect localization in packaged integrated circuit subsystems.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Until recently, the ongoing quest of the semiconductor industry was to improve the performance of integrated circuits (xe2x80x9cICsxe2x80x9d) before the integrated circuit was placed into a package and hermetically sealed from the environment. However, advancements in the performance in integrated circuits may now be limited by the technology by which the circuits are packaged. Improving packaging of integrated circuits may involve increasing the package density (i.e., pin-out) and improving the package performance (i.e., electrical conductance and signal speed).
Device failure or performance impairment can occur if a trace conductor, or group of trace conductors, is not properly conducting electrical signals due to a defect in the trace conductor. There are two basic types of defects that may occur when trace conductors are formed. Missing material defects may occur when a conductive structure is formed which is missing some portion of its conductive material. Such a defect may cause the formation of an xe2x80x9copenxe2x80x9d structure, or break in the conductive pathway of the trace conductor, and is indicated by a measurement of large electrical resistance across the trace conductor. There are several ways an open can occur, either at the terminal sites or along the length of a trace conductor. For instance, the solder balls or solder bumps may have been improperly attached or may have experienced critical mechanical strain due to thermal expansion or package mishandling. There may also be micro-cracks, or other breaks, in the terminals or trace conductors within the substrate. There could be manufacturing defects such as, incomplete vias, missing vias, or misaligned vias between the substrate layers. Further, electromigration could cause cracks to form in the solder joints or in the trace conductor pathways within the substrate. Similarly, an extra material defect may occur when a conductive structure includes material extending beyond the predefined boundaries. Such material may extend to another conductive structure causing an electrical xe2x80x9cshortxe2x80x9d to be formed between the two conductive structures. This type of defect may be indicated by a very low resistance measurement between two or more different trace conductors. An example of a defect that causes an electrical short includes dendritic branching between trace conductors.
To test and locate the exact source of an electrical discontinuity of a trace conductor requires the destructive dismantling of the package and is typically a final step in failure analysis of such devices. A trace conductor, or group of trace conductors, associated with a failing I/O pin will first be pinpointed as a source of electrical pathway discontinuity by preliminary failure analysis testing. Subsequently, localization of the defect may be performed by one of several techniques, such as optical inspection, electrical testing, or other non-destructive evaluations.
One such method for isolating defects in package substrates involves optical inspection. Once a defect is located visually, it is often necessary to test the electrical continuity of the trace by mechanical probing. This is accomplished by first removing the semiconductor chip so as to expose the solder bumps encapsulated in the underfill material beneath the IC. An electrical testing device such as a multi-meter can then be used to measure the resistance of the trace conductor by connecting the two probe wires of the meter on either end of the trace conductor. Typically, a probe wire is soldered to the trace conductor solder ball terminal on the underside of the board. The other probe wire may have a probe needle attached for making electrical contact with the exposed solder bump at the upper surface of the board. However, problems may arise using this testing method. The defect may be heat-cured during the solder attachment of the probe wire to the solder ball if the defect is physically located at or in proximity to the solder ball. Furthermore, when a probe wire is soldered to a trace conductor solder ball, undue tension on the bottom probe wire may be caused during the parallel lapping process (used to remove subsequent layers of the substrate), and may pull the solder ball away from the substrate or simply cause the wire or joint to break.
As stated above, package-level failure analysis has traditionally been performed by optical inspection followed by mechanical probing. Conventional optical inspection methods for package defects involve direct bright and dark field microscope optical inspection. However, the trace length of I/O lines, which may be as long as 9 mm, complicates the task of detecting micro-cracks by optical inspection. Furthermore, even if a micro-crack is detected, its causality may not always be certain. Direct inspection of I/O traces and vias using Scanning Electron Microscopy (SEM) is impossible due to surface charging, which may hinder detection of micro-cracks. In addition, even though a defect may be located by optical inspection, it may not be an electrical failure. Thus, mechanical probing is typically performed to test the electrical continuity of the trace conductors.
Accordingly, as I/O routing becomes increasingly dense in multi-layer substrate packages, a method of pinpointing defects may be needed to augment and eventually supplant current techniques. Therefore, it may be beneficial to provide a method for charged particle beam-based voltage contrast imaging for localization and isolation of package-level substrate defects.
The above outlined problems may be in large part addressed by a voltage-induced contrast imaging technique adapted to supply an electrical signal to a semiconductor package substrate while imaging the substrate with a charged particle beam-based imaging system. The semiconductor package may be a Ball Grid Array (BGA) package designed to receive an integrated circuit. The integrated circuit may be inverted and coupled to the semiconductor package using flip-chip connection techniques. The substrate may be single or multi-layered. The package substrate may include trace conductors arranged between electrical terminals, which may be formed on the package substrate surface. The electrical terminals of the package substrate may be coupled to I/O pins of an integrated circuit by attachment solder bumps.
A test may be conducted prior to removing the IC from the surface of the package substrate. Such testing may include transmitting an electrical pulse along a trace conductor on the surface of the package substrate. Electrical resistance may be measured across the trace conductor to determine whether a defect resides on the surface of the substrate or on an inner layer of the substrate. A failing I/O pin of a semiconductor package may be determined as a source of electrical pathway discontinuity due to a defect in a corresponding trace conductor or group of trace conductors. The package may be prepared for preliminary failure analysis by removing the overlying integrated circuit to expose attachment solder bumps configured within underfill material. If the substrate is a multi-layer substrate, upper layers may be sequentially removed. Measuring the electrical continuity between the trace conductors associated with a failing I/O pin may indicate a defect on a layer of the package substrate.
The package substrate may be mounted in a test fixture. The test fixture may be adapted to expose a backside surface of the substrate to a moveable probe pin attached to a lower part of the fixture. The probe pin may contact an electrical terminal on the back surface of the substrate while a probe needle contacts the corresponding electrical terminal of the trace conductor on a front side surface of the substrate. A test device may be connected between the probe pin and the probe needle and may be used for testing the trace conductor electrical properties. For example, the test device may be a multi-meter configured to measure the electrical resistance of the trace conductor between two layers of the package substrate. If testing measures a low inter-level resistance, a subsequent layer of the package substrate may be removed, and a trace conductor on the underlying substrate layer may be electrically tested. In one embodiment, removal of substrate layers may be achieved by mechanical grinding on a polishing wheel. In another embodiment, removal of substrate layers may be achieved by ashing the substrate layer. This process may be repeated until the defect is located on a layer of the package substrate.
Once the defect is located, an upper surface of the substrate may be an upper surface of the layer on which the defect resides. Also, the trace conductors of the layer may be exposed on the upper surface of the substrate. The substrate may be mounted in a load module, and the substrate may be prepared for optical inspection. Once the substrate is loaded into the load module, a charged particle imaging device may be used to image at least a portion of the package substrate. In one embodiment, the charged particle imaging device may be a Focused Ion Beam (FIB) system. In another embodiment, the charged particle imaging device may be a Scanning Electron Microscopy (SEM) system. In this manner, an image of the semiconductor package may be obtained by supplying a beam of charged particles to at least a portion of the package substrate. The beam of charged particles may cause an emission of charged particles in the traces that are conducting electricity, such that emission may cause the conducting traces to appear to brighten. Likewise, traces that are not conducting electricity may absorb charged particles, such that absorption may cause the non-conducting traces to appear to darken. Thus, the brightening and darkening of traces may produce a voltage-induced contrast image of a trace conductor corresponding to a failing pin of an integrated circuit.
The beam-based image may be focused with the beam-based system""s internal focusing tools. Upon achieving an acceptable image, an electrical signal may be supplied to the trace conductors on the layer of the substrate in which the defect may be located. The electrical signal may be an alternating signal supplied by a function-generating device. The electrical signal may further be a square wave, having sharp transitional points to create an electrical pulse, which may serve to turn the signal xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d in an alternating fashion. An acceptable image of the trace conductors during application of the alternating signal may be acquired by altering brightness and contrast parameters with the internal image tools of the beam-based system.
The alternating square-wave signal may produce a toggling effect in the trace conductor. For example, the alternating square-wave signal supplied to the trace conductor on a layer of the package substrate may produce an electrical pulse. The pulse if may vary the electrical signal between on/off states. The xe2x80x9conxe2x80x9d state may cause a conducting trace in the image to brighten, while the xe2x80x9coffxe2x80x9d state may cause a nonconducting trace in the image to darken. Therefore, toggling may indicate that a trace is conducting the electrical signal, whereas a cease in toggling may indicate that a trace is not conducting the electrical signal. In this manner, the cessation of a previously toggling signal may indicate the presence of an electrical open or break in the electrical continuity of the trace. Similarly, simultaneous toggling of two or more electrically conducting traces, having substantially identical contrasts, may indicate an electrical short between the traces. Consequently, a Capacitive Coupling Voltage Contrast (CCVC) image may indicate a defect corresponding to an electrical discontinuity in a trace conductor on a given layer of the package substrate.
An additional embodiment relates to, a method for detecting electrical defects in a semiconductor package. The method may include producing a CCVC image of a portion of the semiconductor package. The method may also include detecting electrical defects using the voltage-induced contrast image produced by the beam-based imaging system. For example, the method may include determining if micro-cracks in the trace conductor are electrical or non-electrical defects using the voltage-induced contrast image produced by the beam-based imaging system. Producing the image of the portion of the semiconductor package may include applying a signal to a trace conductor of a package substrate of the semiconductor package as described above. The signal may induce a contrast toggling within a trace conductor, which may be imaged with a charged particle imaging device. Such imaging may create a voltage-induced contrast image of at least a portion of the semiconductor package.
In addition to the methods described above, a system configured to detect electrical defects in a semiconductor package is contemplated herein. The system may include a charged particle imaging device configured to produce an image of a portion of the semiconductor package. The system may also include a function generator configured to supply a signal to a trace conductor on a portion of the semiconductor package. The signal from the function generator may be an alternating signal, and more particularly, the signal may be a square wave. The signal may be supplied to the trace conductor while imaging a portion of the semiconductor package with the charged particle imaging device. The image produced by the charged particle imaging device may include a brighter trace conductor if the trace conducts the signal, and may include a darker trace conductor if the trace does not conduct the signal. In this manner, the charged particle imaging device may be further configured to produce a voltage-induced contrast image of the trace conductor. The function generator may also be coupled to an oscilloscope. The oscilloscope may be configured to monitor the signal supplied to the trace conductor by the function generator.